1. Field of the Invention
The present invention generally relates to signal processing circuits and demodulator circuits, and more particularly to a signal processing circuit for eliminating noise from an input signal obtained as a result of binarizing, or converting into binary form, a PSK (phase shift keying)-modulated wobble signal and to a demodulator circuit for demodulating the wobble signal.
2. Description of the Related Art
Conventionally, tracks provided for information recording and reproduction on a recording-type optical disk such as a CD (compact disk) or a DVD (digital versatile disk) meander radially to form a wobble. An optical disk unit includes an optical head that opposes the surface of the disk attached to the optical disk unit. The optical head records information on the disk by emitting a laser beam thereonto, and outputs a reproduction signal corresponding to information recorded on the disk by receiving a reflected light therefrom. The information reproduced by the optical head includes a signal resulting from the wobble formed on the disk. Hereinafter, this signal is referred to as a wobble signal. The optical disk unit extracts the wobble signal from the information reproduced by the optical head.
The wobble is formed sinusoidally on the disk in accordance with digital address information indicating positions on the disk. Therefore, the wobble signal extracted by using the optical head has a sinusoidal waveform. Accordingly, in order to obtain the address information indicating positions on the disk, it is necessary to convert the sinusoidal wobble signal accurately to digital data.
FIG. 1 is a block diagram showing a conventional signal processing circuit 100 for converting the sinusoidal wobble signal to a digital signal. FIG. 2 is a timing chart of signals in the signal processing circuit 100 of FIG. 1. As shown in FIG. 1, the signal processing circuit 100 includes an edge detector circuit 102. The sinusoidal wobble signal extracted by using the optical head is supplied to the edge detector circuit 102 as indicated by (a) of FIG. 2. The edge detector circuit 102 first compares the supplied sinusoidal wobble signal with a zero level. Then, the edge detector circuit 102 generates a binary signal that is HIGH (at a high level) when the sinusoidal wobble signal is above the zero level and is LOW (at a low level) when the sinusoidal wobble signal is below the zero level as indicated by (b) of FIG. 2. Thereafter, the edge detector circuit 102 generates a pulse-like edge signal corresponding to the rising and falling edges of the binary signal as indicated by (c) of FIG. 2.
As shown in FIG. 1, a counter circuit 104, a latch circuit 106, and a digital low-pass filter (LPF) 108 are connected to the edge detector circuit 102. The edge signal generated in the edge detector circuit 102 is supplied to the counter circuit 104, the latch circuit 106, and the digital LPF 108. A reference clock signal is supplied to the counter circuit 104. The counter circuit 104 counts the number of reference clock pulses, and is cleared to zero, or sets the count value of the reference clock pulses to zero, as indicated by (d) of FIG. 2 when the edge signal is supplied from the edge detector circuit 102 to the counter circuit 104.
The counter circuit 104 is connected to the latch circuit 106. The counter circuit 104 supplies its count value to the latch circuit 106. The latch circuit 106 latches the count value when the edge signal is supplied from the edge detector circuit 102 to the latch circuit 106. The latch circuit 106 is connected to the digital LPF 108. The digital LPF 108 is supplied with the count value that is supplied to the latch circuit 106. When the edge signal is supplied from the edge detector circuit 102 to the digital LPF 108, the digital LPF 108 performs digital low-pass filtering on the count value supplied from the latch circuit 106 so as to eliminate noise components from the count value. The signal processed in the digital LPF 108 is demodulated so that the address information converted to the wobble signal is extracted.
FIG. 3 is a diagram showing a variation over time of the sinusoidal wobble signal resulting from the wobble formed on the disk, the sinusoidal wobble signal being extracted in the optical disk unit. FIG. 4 is a diagram showing a variation over time of the wobble signal extracted in the optical, disk unit when the wobble formed on the disk is PSK-modulated in accordance with the address information of the disk.
Normally, noise is superimposed on the sinusoidal wobble signal resulting from the wobble formed on the disk. Therefore, the wobble signal crosses the zero level a plurality of times near the crossing points of the wobble signal and the zero level as shown in FIG. 3. If the wobble is PSK-modulated, in some cases, the wobble signal based on the PSK-modulated wobble, at the time of phase inversion, goes above the zero level when the wobble signal should be maintained at or below the zero level or goes below the zero level when the wobble signal should be maintained at or above the zero level as shown in FIG. 4.
Accordingly, in the configuration of binarizing the wobble signal by comparing the wobble signal with the zero level and extracting the address information converted to the wobble signal based on the number of the rising and falling edges of the binary wobble signal as in the conventional signal processing circuit 100, the number of falling and rising edges is affected by the noise. Therefore, according to the above-described conventional method, it is difficult to detect the address information with accuracy based on the wobble signal.